1. Field of the Invention
The present invention relates to a power up signal generator, and more particularly, to a power up signal generator with stable operation over a range of operating temperatures.
2. Description of the Related Art
In general, a semiconductor memory device may be equipped with a power up signal generator so that the device is not enabled to operate immediately in response to the application of an external source voltage. Instead, the power up signal generator enables the device to operate after the external source voltage level rises above a threshold. The time required for the external source voltage to reach the threshold can allow for internal circuit components to stabilize at their proper states. Thus, by preventing its internal circuits from operating before the external source voltage level has become stabilized at a normal operating level, the power up signal generator helps prevent latch-ups, or other undesired effects, from corrupting the data contents of the memory device, thus enhancing the reliability of the overall chip.
The power up signal generator senses a rise in the level of the external source voltage as it is initially applied, and outputs a constant “low” level power up signal. When the external source voltage source has risen above the threshold level, the power up signal generator changes the output power up signal to a “high” state. Subsequently, if the voltage level of the applied external source voltage drops below the threshold, the power up signal generator again outputs a “low” level power up signal until the level of the external source voltage once again has risen above the threshold and is stabilized. The power up signal generator is usually implemented as an independent circuit at an initial stage of a pipeline to provide the power up signal as an internal supply voltage for subsequent internal circuits in the memory device. The power up signal is mainly used to initially activate these circuits.
A power up pulse generating circuit is disclosed in U.S. Pat. No. 5,030,845, which does not include a node connected to both a static pull-down path and a static pull-up path, thereby forming a linear circuit.
Another power up pulse generating circuit is disclosed in Japanese Laid-Open Patent Application No. 7-57474, which generates a power up signal after an applied external source voltage has completely risen to its full amount during power-up.
FIG. 1 is a circuit diagram illustrating a conventional power up signal generator.
The power up signal generator of FIG. 1 is constructed of a level sensing part 10 for sensing a level of an applied external source voltage VDD, and inverters 12, 14 for buffering a level sense signal output from the level sensing part 10. Inverter 14 outputs a power up signal VccH.
The level sensing part 10 includes an NMOS transistor 20, which is diode-connected (i.e., its gate is connected to its drain). The NMOS transistor 20 is positioned between the external source voltage source VDD and an output node N1. A resistor 22 is connected between a source of the NMOS transistor 20 and a ground.
While inverters 12, 14 respectively have the same circuit components and configuration; thus FIG. 1 only illustrates the components and configuration of inverter 12 in detail. As shown, the inverter 12 is constructed of a PMOS transistor 24 and an NMOS transistor 26 connected together in series between the applied external source voltage VDD and the ground. The gates of these transistors 24 and 26 are connected to the node N1. The source of PMOS transistor 24 and NMOS transistor 26 is connected to an output node of the inverter 12. The inverter 14 is connected to receive the output signal of the inverter 12.
As the external source voltage VDD is initially applied, it rises gradually. The diode-connected NMOS transistor 20 is turned off, and a low voltage signal is applied to the node N1, until the external source voltage VDD reaches a threshold voltage Vth of the NMOS transistor 20. The low signal applied to the node N1 turns on the PMOS transistor 24 of the inverter 12, thus causing the low signal to be inverted and output as a high signal. The high output signal of the inverter 12 is inverted by the inverter 14. The low signal output by the inverter 14 is applied to the gate of a PMOS transistor 16. The low signal turns on the PMOS transistor 16, whose source maintains the voltage of a latch 18 at an initial voltage level, in order to prevent errant operation of the memory device.
FIG. 2 illustrates the general operation of a power up signal generator as external source voltage VDD rises. Referring to FIG. 2, as the level of external source voltage VDD gradually rises to the threshold voltage Vth of the NMOS transistor 20, the diode-connected NMOS transistor 20 is turned on, and the resistor 22 controls a current flow. After the NMOS transistor 20 is turned on, it operates as a diode; thus, the voltage applied to the node N1 is the difference between the external source voltage and the threshold voltage of the NMOS transistor 20 (VDD−Vth).
Thereafter, the external source voltage VDD continues to rise until the voltage applied at node N1 (VDD−Vth) meets the threshold voltage of the NMOS transistor 26 (also Vth) in the inverter 12, thus turning on the NMOS transistor 26. The level of the external source voltage VDD required to turn on the NMOS transistor 26 is referred to as the trip voltage Vtrip. Since the threshold voltages Vth of the NMOS transistors 20 and 26 are the same, the trip voltage is twice the threshold voltage Vth.
When the NMOS transistor 26 is turned on, the inverter 12 outputs a low signal. The low signal output from the inverter 12 is received by the inverter 14, which inverts the signal to produce a high signal, i.e., the external source voltage VDD, as output signal VccH. The time required for the inverter 14 to output a high signal VccH in response to the low input signal from the inverter 12 allows the external source voltage source VDD to rise closer to the normal operating voltage. When the inverter 14 outputs the power up signal VccH as the high signal (VDD) as shown in FIG. 2, the internal circuits of the memory device are activated for normal operation.
In such a conventional power up signal generating circuit, the difference between the normal level of the external source voltage VDD and the trip voltage Vtrip is rather small. For example, where the normal operating level of the external source voltage is 1.8V and the operating temperature of the memory device is −5° C., the trip voltage Vtrip may be set at 1.3V (where Vth is 0.65V). Thus, if the applied external source voltage VDD were to be lowered to 1.6v the trip voltage Vtrip of 1.3V would be very high relative to VDD. Accordingly, minor fluctuations in the external source voltage VDD that dip below the trip voltage Vtrip may cause the power up signal VccH to switch to a low level, thereby disrupting the operation of the overall memory device.
Furthermore, in MOSFET transistors, the threshold voltage Vth can be affected by changes in the operating temperature. For example, the threshold voltage of an NMOS transistor typically decreases by about 200 mV in response to a temperature increase of 100° C. Since the conventional power up signal generator described above has a trip voltage Vtrip equal to twice the threshold voltage 2*Vth, the trip voltage Vtrip of the conventional power up signal generator is twice as sensitive to changes in the operating temperature. Accordingly, the trip voltage can be lowered by 400 mV according to an increase of about 100° C. Such sensitivity to temperature can cause unstable operation for conventional power up signal generators.